How the Bosch process alternates etch and passivation to cut deep, vertical features in silicon, what limits it, and what to check on a used DRIE tool.
Deep reactive ion etching (DRIE) is how MEMS, microfluidics, through-silicon vias and many photonic and sensor structures get their deep, vertical walls.
The most widely used variant is the Bosch process, developed at Robert Bosch GmbH in the 1990s and licensed to equipment makers, including STS, whose Multiplex ICP ASE became a common DRIE platform in university and pilot-line cleanrooms. Many of these tools are now on the used market.
To run one well, or to judge one before buying, it helps to understand what the process does and where it goes wrong. This article covers the mechanism, the parameters that matter and the typical wear points on a used DRIE system.
The Bosch process alternates two short plasma steps in an inductively coupled plasma (ICP) chamber, typically switching every few seconds.
In the next etch step, ion bombardment removes the polymer from horizontal surfaces, mainly the bottom of the feature, while the sidewalls stay protected. Silicon at the bottom etches, then the cycle repeats. The result is a deep, near-vertical feature built up from many small, slightly isotropic etch steps.
Because the etch step uses a dense ICP plasma, rates of several micrometres per minute are common on older tools for moderate exposed areas, depending on configuration and recipe.
The cycling leaves a signature on the sidewall: small scallops, one per cycle. Their depth depends on the length of the etch step. Shorter steps give smoother walls but lower average rate, because more time is spent on passivation and switching. Applications such as optical or fluidic channels may need smoother walls than a MEMS spring.
Profile angle is controlled mainly by the balance between etch and passivation. More passivation gives positively tapered walls; too little lets the etch undercut and bow the profile. Bias power on the platen and chamber pressure shift the balance too.
Selectivity to photoresist and silicon dioxide masks is high compared with conventional RIE, which is why a few micrometres of resist can mask deep etches. Ratios depend strongly on the recipe and exposed area, so check them on your own pattern rather than relying on published figures. For very deep or long etches, an oxide or metal hard mask is safer.
Three effects limit what a Bosch process can do.
Aspect-ratio-dependent etching (ARDE). Narrow features etch more slowly than wide ones, because fewer radicals and ions reach the bottom. On a wafer with mixed feature sizes, wide trenches finish first. Designers often add dummy structures or keep trench widths uniform to manage this.
Loading. The total exposed silicon area changes the etch rate. A wafer with 50 % open area etches more slowly than one with 5 %, so a recipe tuned on one mask may not transfer to another. Note the open area when qualifying a recipe.
Notching. When etching silicon-on-insulator (SOI) wafers down to the buried oxide, charge builds up on the insulator and deflects ions sideways, cutting a notch at the base of the structure. This matters for MEMS devices that rely on the device layer's geometry. Later DRIE tools offer a pulsed low-frequency bias on the platen to reduce notching. On older tools, timing the etch carefully and using endpoint detection help.
Bosch etches are often timed, but timing is fragile when loading, chamber condition or mask thickness change. Optical emission endpoint detection monitors the plasma for the change in signal when silicon clears, which is useful for SOI and for through-wafer etches onto a carrier. Laser interferometry can track depth on suitable test structures.
For a shared research tool, endpoint is worth fitting if it is not already present. It reduces over-etch, protects the buried oxide on SOI wafers and makes results less dependent on the operator. Our endpoint detection page describes the options we fit to older ICP tools.
Wafer temperature is the other control that is often overlooked. The wafer is cooled through helium backside gas against a chilled platen. A poorly sealed clamp or a leaking helium circuit lets the wafer heat up, which changes the polymer behaviour and the profile, and can burn resist. Check the helium leak rate as part of every qualification.
The main alternative to Bosch is cryogenic DRIE. Instead of alternating steps, it runs SF6 and O2 together with the wafer cooled far below 0 °C, often around −100 °C. At that temperature, a thin oxyfluoride layer forms on the sidewalls and protects them while the bottom etches. The walls come out smooth, without scallops, which suits optical and nanoscale structures.
The cost is sensitivity. Small changes in wafer temperature or oxygen flow alter the profile, resist can crack at low temperature, and the platen needs liquid nitrogen cooling. For most MEMS and through-wafer work, Bosch remains the more forgiving process, and it is what most used DRIE tools are built to run.
DRIE tools work hard. The passivation step coats the chamber as well as the wafer, and the fast gas switching cycles valves and mass flow controllers continuously. On a used system such as the STS Multiplex ICP ASE, the usual wear points are:
Ask for an etch test on a standard pattern with rate, selectivity and a cross-section, and compare it with the tool's historical data if available.
We inspect, refurbish and install DRIE systems from our etch range, including chamber stripping and cleaning, gas switching checks, clamp and helium circuit repair, and endpoint retrofits. Send us your target depth, feature sizes and mask, and we will suggest whether a used Bosch tool fits your process.
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